Multi-Processor System with Distributed Mailbox Architecture and Processor Error Checking Method Thereof

ABSTRACT

A multi-processor system with a distributed mailbox architecture and a processor error checking method thereof are provided. The multi-processor system comprises a plurality of processors, each of the processors is correspondingly configured with an exclusive mailbox and an exclusive channel, and the processor error checking method comprises the following steps. When a first processor of the processors needs to communicate with a second processor, the first processor writes the data into the exclusive mailbox of the second processor through a public bus; and when the exclusive mailbox of the second processor has receiving the data, the exclusive mailbox of the second processor starts timing, and until the timing result exceeds a threshold value, the exclusive mailbox of the second processor sends a timeout signal to the second processor, and after receiving the timeout signal, the second processor resets the first processor.

FIELD OF THE INVENTION

The present invention relates to a multi-processor system, and moreparticularly to a multi-processor system with a distributed mailboxarchitecture and a processor error checking method thereof.

BACKGROUND OF THE INVENTION

In conventional multi-processor systems, there is usually a sharedmemory used as a communication scheme. For example, please refer to FIG.1, which is a functional block diagram of a conventional multi-processorsystem. A multi-processor system 1 comprises a shared memory 110 and aplurality of processors, such as processors CPU_0 to CPU_N. However,since the shared memory 110 and each of the processors are coupled to asame public bus, when there are more than one of the processors read andwrite the shared memory 110, the multi-processor system 1 needs to makea queue schedule of the public bus, resulting in the waiting of thepublic bus and degrading of the overall system performance.

SUMMARY OF THE INVENTION

In view of this, the embodiments of the present invention provide amulti-processor system with a distributed mailbox architecture and acommunication method thereof. The multi-processor system comprises aplurality of processors, each of the processors is correspondinglyconfigured with an exclusive mailbox and an exclusive channel, and thecommunication method comprises the following steps. When a firstprocessor of the processors needs to communicate with a secondprocessor, the first processor writes data into the exclusive mailbox ofthe second processor through a public bus; and when the writing of thedata has completed, the exclusive mailbox of the second processor sendsan interrupt signal to the second processor, after receiving theinterrupt signal, the second processor reads the data in the exclusivemailbox through the corresponding exclusive channel.

In addition, the embodiments of the present invention further provide aprocessor error checking method. The processor error checking method canbe similarly executed in the aforementioned multi-processor system, andcomprises the following steps. When a first processor of the processorsneeds to communicate with a second processor, the first processor writesthe data into an exclusive mailbox of the second processor through apublic bus; and when the exclusive mailbox of the second processorreceives the data, the exclusive mailbox of the second processor startstiming, and until the timing result exceeds a threshold value, theexclusive mailbox of the second processor sends a timeout signal to thesecond processor, and after receiving the timeout signal, the secondprocessor resets the first processor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of a conventional multi-processorsystem;

FIG. 2 is a functional block diagram of a multi-processor system with adistributed mailbox architecture according to an embodiment of thepresent invention;

FIG. 3A is a flowchart related to a first processor in a communicationmethod according to an embodiment of the present invention;

FIG. 3B is a flowchart related to a second processor in thecommunication method according to an embodiment of the presentinvention;

FIG. 4 is a functional block diagram of an exclusive mailbox in themulti-processor system of FIG. 2; and

FIG. 5 is a flowchart of a processor error checking method according toan embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In the following, the present invention will be described in detail byvarious embodiments with the accompanying figures. However, the conceptsof the present invention may be embodied in many different forms andshould not be construed as being limited to the illustrative embodimentsset forth herein. In addition, the same reference numerals in thedrawings may be used to represent similar elements.

Please refer to FIG. 2, which is a functional block diagram of amulti-processor system with a distributed mailbox architecture accordingto an embodiment of the present invention. As shown in FIG. 2, amulti-processor system 2 comprises a plurality of processors, and eachof the processors is correspondingly configured with an exclusivemailbox and an exclusive channel. For example, a processor CPU_0 isconfigured with an exclusive mailbox MB_0 and an exclusive channel 210,a processor CPU_1 is configured with an exclusive mailbox MB_1 and anexclusive channel 211, and so on, and a processor CPU_N is configuredwith an exclusive mailbox MB_N and an exclusive channel 21N. It can beunderstood that the above mentioned N is any positive integer greaterthan 1, and each of the exclusive mailboxes can be composed of anystorage medium, such as static random access memory (SRAM) or dynamicrandom access memory (DRAM), however, the present invention is notlimited thereto.

As shown in FIG. 2, since all the processors and the exclusive mailboxesare coupled to a same public bus, in this embodiment, when the firstprocessor of the processors, such as the processor CPU_0 writes datainto the second processor, for example, the processor CPU_1, the firstprocessor CPU_0 writes the data into the exclusive mailbox MB_1 of thesecond processor CPU_1 through the public bus, and the written data isread by the second processor CPU_1 from its exclusive mailbox MB_1,thereby communication between the multi-processors is done in thismethod. It should be explained that, before the first processor CPU_0writes data into the exclusive mailbox MB_1 of the second processorCPU_1, the first processor CPU_0 preferably first confirms whether theexclusive mailbox MB_1 of the second processor CPU_1 has a sufficientstorage space for storing the data, and if so, the first processor CPU_0writes the data into the exclusive mailbox MB_1 of the second processorCPU_1 through the public bus, and when the writing of the data hascompleted, the exclusive mailbox MB_1 preferably sends an interruptsignal IS to the second processor CPU_1, or a register (not shown) ofthe second processor CPU_1 can be set to inform the second processorCPU_1 that the data is currently written into its exclusive mailboxMB_1. After receiving the interrupt signal IS or reading a value of theregister, the second processor CPU_1 reads the data in its exclusivemailbox MB_1 through the corresponding exclusive channel 211, and thenperforms related processing on the data.

In other words, each of the processors is configured with thecorresponding exclusive mailbox, instead of the processors sharing thesame mailbox or memory, and therefore, the management procedure ofstoring data in the exclusive mailbox can be significantly simplified.Moreover, since each of the processors accesses the data in itsexclusive mailbox through the corresponding exclusive channel, when eachof the processors reads its exclusive mailbox, it does not need to bedone via the public bus in the this embodiment, so that it does notoccupy the resources of the public bus and can improve the overallsystem performance. In addition, when any one of the processors needs towrite data into its exclusive mailbox, besides the processor can writedata through the exclusive channel to avoid occupying the resources ofthe public bus, the processor can also write data into its exclusivemailbox through the public bus.

It should be noted that, since the multi-processor system 2 of thisembodiment is preferably implemented by a data storage device, when ahost (not shown) sends host commands to the multi-processor system 2, afront end (FE) processor of the multi-processor system 2, such as theprocessor CPU_0, is the first to process the host commands, such asobtaining the host commands from a transmission interface and sortingthem, and then writing the processed host commands into a back end (BE)processor for communication, for example, into the exclusive mailboxMB_1 of the processor CPU_1, causing the processor CPU_1 to perform aspecific function according to the host commands processed by the frontend processor. That is to say, the above-mentioned “data” can refer tothe host commands processed by the front end processor, or simplycommands transmitted between the processors, but the present inventionis not limited thereto.

Similarly, in this embodiment, each of the processors preferablyperforms data transmission on the public bus according to an advancedextensible interface (AXI) protocol, for example, when the firstprocessor writes data into the exclusive mailboxes of the otherprocessors, the public bus preferably has an arbiter (not shown) tohandle the writing requests of all or most of the processors, and thewriting request of the first processor is sequentially permittedaccording to the writing requests, the priority among the processors, orthe order in which the writing requests are sent, and the sequence amongthe processors, etc. Therefore, after the writing request is permitted,the first processor can write the data into the exclusive mailboxes ofthe other processors through the public bus, and the first processorwhose writing request has not been permitted, can access the public busonly after the writing request is permitted.

Additionally, each of the processors preferably reads the data in itsexclusive mailbox according to a self register protocol. For example,after data is written into the exclusive mailbox of the secondprocessor, the exclusive mailbox sends the interrupt signal IS to thesecond processor. Then, the second processor can read the data in itsexclusive mailbox according to the self register protocol, and after thedata is read, the second processor can further inform its exclusivemailbox to delete or invalidate the data according to the self registerprotocol. In this way, the exclusive mailbox can reclaim the storagespace occupied by the old data for storing new data. Correspondingly, inthis embodiment, the first processor preferably writes one piece or aplurality of pieces of data into the exclusive mailbox of the secondprocessor, and the second processor preferably reads one piece or aplurality of pieces of data from its exclusive mailbox, but the presentinvention is not limited thereto.

In addition, in this embodiment, each of the exclusive mailboxes canfurther output a status signal to indicate whether it has a sufficientstorage space to store data, and each of the exclusive mailboxespreferably receives the status signals outputted from the otherexclusive mailboxes. For example, the exclusive mailbox MB_0 outputs astatus signal ST_0, and the exclusive mailbox MB_0 receives statussignals ST_1 to ST_N outputted from the exclusive mailbox MB_1 to theexclusive mailbox MB_N, respectively. Correspondingly, the exclusivemailbox MB_1 outputs the status signal ST_1, and the exclusive mailboxMB_1 receives the status signals ST_0 and ST_2 to ST_N respectivelyoutputted from the exclusive mailbox MB_0 as well as the exclusivemailbox MB_2 to the exclusive mailbox MB_N, and so on; and the exclusivemailbox MB_N outputs the status signal ST_N, and the exclusive mailboxMB_N receives the status signal ST_0 to a status signal ST_N−1 outputtedfrom the exclusive mailbox MB_0 to an exclusive mailbox MB_N−1,respectively. Therefore, when the first processor, for example, theprocessor CPU_0 needs to communicate with the second processor, such asthe processor CPU_1, the first processor CPU_0 can confirm whether theexclusive mailbox MB_1 has a sufficient storage space to store the dataaccording to the status signal ST_1 received by its exclusive mailboxMB_0. Or, in other embodiments, the status signals of all the exclusivemailboxes are preferably outputted to each of the processors, so thatthe first processor CPU_0 can directly determine whether to write datainto the exclusive mailbox MB_1 according to the received status signalST_1.

For example, each of the status signals is preferably implemented by abit value, and when the bit value is 0, the exclusive mailboxrepresented by the status signal has sufficient storage space forstoring data, and when the bit value is 1, the exclusive mailboxrepresented by the status signal does not have enough storage space forstoring data, but the present invention is not limited thereto. Next,the way of implementation of the communication method of this embodimentwill be further described with reference to FIG. 3A and FIG. 3B. FIG. 3Ais a flowchart related to the first processor in the communicationmethod according to the embodiment of the present invention; and FIG. 3Bis a flowchart related to the second processor in the communicationmethod according to the embodiment of the present invention. Since thedetails are also the same as described above, they will not be repeatedherein again.

As shown in FIG. 3A, when the first processor, for example, theprocessor CPU_0 needs to communicate with the second processor, such asthe processor CPU_1, in step S110, the first processor CPU_0 reads thestatus signal ST_1 outputted by the exclusive mailbox MB_1 from theexclusive mailbox MB_0, and in step S120, according to the status signalST_1, determines whether the exclusive mailbox MB_1 has sufficientstorage space for storing the data; if so, continuing to perform stepS130; and if not, returning to perform step S110. That is, using theforegoing content as an example, before the exclusive mailbox MB_1 hasenough storage space to store the data, that is, when the status signalST_1 is 1, the first processor CPU_0 continues to perform a loop ofsteps S110 and S120, until it is determined that the status signal ST_1is 0.

It should be explained that, in this embodiment, each of the exclusivemailboxes can preferably determine the status signal generated as 0 or 1by checking whether its storage space is lower than a preset value, butthe present invention is not limited thereto. In summary, the presentinvention does not limit the specific implementation of each of theexclusive mailboxes to generate or output the status signal, and thoseskilled in the art should be able to make related designs according toactual needs or applications. In addition, it should be understood thatthe content format in the exclusive mailbox is preferably defined by thefirmware of the multi-processor system 2, so that this embodiment caneasily change the content format of the data, thereby achieving anarchitecture that is easy to extend and flexible. Next, in step S130,the first processor CPU_0 writes the data into the exclusive mailboxMB_1 through the public bus, and when the writing of the data hascompleted, the exclusive mailbox MB_1 sends the interrupt signal IS tothe second processor CPU_1.

In this embodiment, the interrupt signal IS is also preferablyimplemented by a bit value. For example, when the second processor CPU_1receives and determines that the interrupt signal IS sent by theexclusive mailbox MB_1 is 1, the second processor CPU_1 can know thatnew data has been successfully written into its exclusive mailbox MB_1.Therefore, as shown in FIG. 3B, in step S140, the second processor CPU_1waits for the exclusive mailbox MB_1 to send the interrupt signal IS,and in step S150, determines whether the interrupt signal IS isreceived; if so, continuing to perform step S160; and if not, returningto perform step S140. That is to say, using the foregoing content as anexample, before the writing of the data is completed, that is, when theinterrupt signal IS is not 1, the second processor CPU_1 continues toperform a loop of step S140 and step S150, until the interrupt signal ISof 1 is received. Finally, in step S160, the second processor CPU_1reads the data in the exclusive mailbox MB_1 through the correspondingexclusive channel 211.

On the other hand, the present invention further provides another way ofimplementation of the exclusive mailbox. Please refer to FIG. 4, whichis a functional block diagram of the exclusive mailbox in themulti-processor system of FIG. 2. It should be noted that, in order tofacilitate the following description, this embodiment will be describedby using only the exclusive mailbox MB_1 of the processor CPU_1 as anexample, but it is not intended to limit the present invention. As shownin FIG. 4, the exclusive mailbox MB_1 comprises a storage space 410, acontrol register 420, and a mailbox controller 430. It should be notedthat the above-mentioned control register 420 and mailbox controller 430can be implemented by solely hardware circuits, or can be implemented byhardware circuits with firmware or software, but the present inventionis not limited thereto. In addition, the above components can beintegrated or separately disposed, but the present invention is notlimited thereto. In summary, the present invention does not limit thespecific implementation of the exclusive mailbox MB_1.

In this embodiment, the storage space 410 is preferably a SRAM, and thefirst-in-first-out (FIFO) queue is preferably used to store(temporarily) the data. A size of the storage space 410 is, for example,1 KB. Under this setting, the storage space 410 can store 64 pieces ofdata of size 16 B, or 32 pieces of data of size 32 B, or 16 pieces ofdata of size 64 B. The control register 420 stores the relevant settingsof the exclusive mailbox MB_1, for example, the control register 420 canbe used to set an interrupt condition of the exclusive mailbox MB_1, andwhen the interrupt condition is satisfied, for example, when one or morethan one pieces of data are successfully written into the mailbox MB_1,the mailbox MB_1 sends the interrupt signal IS to the processor CPU_1.In addition, the mailbox controller 430 is used to write set values intothe control register 420, and manage the storage space 410, and generatethe interrupt signal IS and the status signal ST_1.

In this embodiment, the mailbox controller 430 preferably manages thesize and amount of data in the storage space 410 according to thesettings of the processor CPU_1. If the size of the data is set to 64 B,when the remaining available space of the storage space 410 is less thanor equal to a preset value, for example, 64 B (i.e. the storage space410 can only store one more piece of data), the mailbox controller 430generates the status signal ST_1 of 1. In this way, all the processorscan no longer write data into the exclusive mailbox MB_1. Then, afterthe processor CPU_1 reads the data stored in the exclusive mailbox MB_1,the exclusive mailbox MB_1 reclaims the storage space of the read data,so that the remaining available space is increased to, for example, 128B. At this time, since the remaining available space is larger than thepreset value, the mailbox controller 430 generates the status signalST_1 of 0, and when the status signal ST_1 is 0, the processor CPU_0that needs to write data into the exclusive mailbox MB_1 can make awriting request to the public bus, and after the writing request ispermitted, the processor CPU_0 can write data into the exclusive mailboxMB_1.

In other words, as shown in FIG. 4, when the processor CPU_0 needs tocommunicate with the processor CPU_1, the processor CPU_0 determineswhether the exclusive mailbox MB_1 has the sufficient storage space 410to store data according to the received status signal ST_1 outputted bythe exclusive mailbox MB_1. If so, the processor CPU_0 writes data intothe storage space 410 of the exclusive mailbox MB_1 through the publicbus. Then, when the writing of data has completed, the mailboxcontroller 430 of the exclusive mailbox MB_1 generates and sends theinterrupt signal IS to the processor CPU_1. After receiving theinterrupt signal IS, the processor CPU_1 accesses the data in thestorage space 410 through the corresponding exclusive channel 211. Sincethe details are also the same as described above, they will not berepeated herein again.

On the other hand, besides using as a communication scheme between thedifferent processors, the exclusive mailbox provided in this embodimentcan also be used to check whether the processor that writes data has anerror, and assist in resetting the processor with error, in order toprevent the processor from causing the entire multi-processor system 2to be stuck. Therefore, please refer to FIG. 5, which is a flowchart ofa processor error checking method according to the embodiment of thepresent invention. It should be explained that the processor errorchecking method of FIG. 5 can be executed in the multi-processor system2 of FIG. 2, but the present invention does not limit the processorerror checking method of FIG. 5 being only able to execute in themulti-processor system 2 of FIG. 2. In addition, the steps in FIG. 5which are the same as those in FIG. 4 are denoted by the same referencenumerals, and thus the details thereof will not be described hereinagain.

As shown in FIG. 5, when the first processor, for example, the processorCPU_0 needs to communicate with the second processor, such as theprocessor CPU_1, in step S110, the first processor CPU_0 reads thestatus signal ST_1 outputted by the exclusive mailbox MB_1, and in stepS120, determines whether the exclusive mailbox MB_1 has sufficientstorage space to store data according to the status signal ST_1; if so,continuing to perform step S130; and if not, returning to perform stepS110. Next, in step S130, the first processor CPU_0 writes the data intothe exclusive mailbox MB_1 through the public bus, and when theexclusive mailbox MB_1 receives the data, in step S510, the exclusivemailbox MB_1 starts timing, and in step S520, determines whether thereceiving of the data has completed, that is, determines whether thewriting of the data has completed; if not, continuing to perform stepS530. It should be noted that, since the operation principle of theexclusive mailbox MB_1 to determine whether the receiving of the datahas completed according to the received data is known to those ofordinary skill in the art, the details of the above step S520 will notbe described herein again.

Then, in step S530, the exclusive mailbox MB_1 of the second processorCPU_1 determines whether the timing result exceeds a threshold value; ifnot, returning to perform step S520; and if yes, continuing to performstep S540 and step S550. In step S540, the exclusive mailbox MB_1 sendsa timeout signal TS to the second processor CPU_1 to inform the secondprocessor CPU_1 that the first processor CPU_0 currently writing thedata has an error, and in step S550, after receiving the timeout signalTS, the second processor CPU_1 resets the first processor CPU_0. Forexample, the second processor CPU_1 preferably sends a reset signal (notshown) to the first processor CPU_0, so that the first processor CPU_0can be reset according to the reset signal, but the present invention isnot limited thereto.

That is, assume that the first processor CPU_0 needs to write 64 B ofdata into the exclusive mailbox MB_1, and after the exclusive mailboxMB_1 receives the data from the first processor CPU_0 and starts timing,if the first processor CPU_0 only writes 24 B of data and stops writing,this means the first processor CPU_0 may have an internal error, whichcauses the first processor CPU_0 to fail to complete the writing of datain time. Therefore, until the timing result exceeds a threshold value,for example, 1000 milliseconds, the exclusive mailbox MB_1 generates thetimeout signal TS to notify the second processor CPU_1, and according tothe first processor CPU_0 indicated by the timeout signal TS, oraccording to information of the request side writing the data, thesecond processor CPU_1 determines the source of data is from the firstprocessor CPU_0 in order to reset the first processor CPU_0. It shouldbe explained that, since the settings of the timing and various types ofdetermining functions are preferably implemented by the mailboxcontroller 430 writing the setting values into the control register 420,and the mailbox controller 430 is preferably controlled by thecorresponding processor CPU_1; therefore, in addition to being used togenerate and output the interrupt signal IS and the status signal ST_1,the mailbox controller 430 can also be used to generate and output thetime-out signal TS.

On the other hand, in step S520, if the exclusive mailbox MB_1determines to have received the data, that is, when the data is writteninto the exclusive mailbox MB_1, this embodiment continues to performsteps S560, S570, and S160. In step S560, the exclusive mailbox MB_1stops and resets the timing to zero, and in step S570, the exclusivemailbox MB_1 sends the interrupt signal IS to the second processorCPU_1. Finally, in step S160, after receiving the interrupt signal IS,the second processor CPU_1 reads the data in the exclusive mailbox MB_1through the corresponding exclusive channel 211. Since the details arealso the same as described above, they will not be repeated hereinagain.

In summary, the multi-processor system with the distributed mailboxarchitecture and the communication method thereof provided by theembodiments of the present invention do not need to have a conventionalshared memory, but are designed to have each of the processors equippedwith the exclusive mailbox, so that communication between the differentprocessors can be achieved by writing data into the exclusive mailbox ofthe mapping processor through the public bus. Since each of theprocessors accesses the data in the exclusive mailbox through theexclusive channel, when each of the processors reads the exclusivemailbox, the embodiments of the present invention will not affect thepublic bus, thereby reducing the usage rate of the public bus, andenhancing the overall system performance. In addition, the processorerror checking method provided by the embodiments of the presentinvention can use the exclusive mailbox to check whether the processorthat writes data has an error, and assist in resetting the processorwith error, in order to prevent the processor from causing the entiremulti-processor system to be stuck.

Note that the specification relating to the above embodiments should beconstrued as exemplary rather than as limitative of the presentinvention, with many variations and modifications being readilyattainable by a person of average skill in the art without departingfrom the spirit or scope thereof as defined by the appended claims andtheir legal equivalents.

What is claimed is:
 1. A multi-processor system with a distributedmailbox architecture, comprising: a plurality of processors, each of theprocessors being correspondingly configured with an exclusive mailboxand an exclusive channel; wherein when a first processor of theprocessors needs to communicate with a second processor, the firstprocessor writes data into the exclusive mailbox of the second processorthrough a public bus; and when the exclusive mailbox of the secondprocessor receives the data, the exclusive mailbox of the secondprocessor starts timing, and until the timing result exceeds a thresholdvalue, the exclusive mailbox of the second processor sends a timeoutsignal to the second processor, and after receiving the timeout signal,the second processor resets the first processor.
 2. The multi-processorsystem as claimed in claim 1, wherein when the first processor needs tocommunicate with the second processor, the first processor confirmswhether the exclusive mailbox of the second processor has a sufficientstorage space to store the data, if so, the first processor writes thedata into the exclusive mailbox of the second processor through thepublic bus.
 3. The multi-processor system as claimed in claim 2, whereineach of the exclusive mailboxes is further used to output a statussignal to indicate whether it has the sufficient storage space to storethe data, and each of the exclusive mailboxes receives the statussignals outputted from the other exclusive mailboxes.
 4. Themulti-processor system as claimed in claim 3, wherein when the firstprocessor confirms whether the exclusive mailbox of the second processorhas the sufficient storage space to store the data, the first processorreads the status signal outputted by the exclusive mailbox of the secondprocessor, and determines, according to the status signal, whether theexclusive mailbox of the second processor has the sufficient storagespace to store the data.
 5. The multi-processor system as claimed inclaim 4, wherein when the exclusive mailbox of the second processor hasreceiving the data, the exclusive mailbox of the second processor stopsand resets the timing to zero, and sends an interrupt signal to thesecond processor, and after receiving the interrupt signal, the secondprocessor reads the data in the exclusive mailbox through the exclusivechannel.
 6. The multi-processor system as claimed in claim 5, whereineach of the exclusive mailboxes further comprises: a control registerfor setting an interrupt condition of the exclusive mailbox; and amailbox controller for managing the storage space as well as generatingthe timeout signal, the interrupt signal and the status signal.
 7. Aprocessor error checking method for executing in a multi-processorsystem, the multi-processor system comprising a plurality of processors,each of the processors being correspondingly configured with anexclusive mailbox and an exclusive channel, and the processor errorchecking method comprising the following steps of: when a firstprocessor of the processors needing to communicate with a secondprocessor, the first processor writing data into the exclusive mailboxof the second processor through a public bus; and when the exclusivemailbox of the second processor receiving the data, the exclusivemailbox of the second processor starting timing, and until the timingresult exceeding a threshold value, the exclusive mailbox of the secondprocessor sending a timeout signal to the second processor, and afterreceiving the timeout signal, the second processor resetting the firstprocessor.
 8. The processor error checking method as claimed in claim 7,wherein when the first processor needs to communicate with the secondprocessor, the first processor confirms whether the exclusive mailbox ofthe second processor has a sufficient storage space to store the data,if so, the first processor writes the data into the exclusive mailbox ofthe second processor through the public bus.
 9. The processor errorchecking method as claimed in claim 8, wherein each of the exclusivemailboxes is further used to output a status signal to indicate whetherit has the sufficient storage space to store the data, and each of theexclusive mailboxes receives the status signals outputted from the otherexclusive mailboxes.
 10. The processor error checking method as claimedin claim 9, wherein when the first processor confirms whether theexclusive mailbox of the second processor has the sufficient storagespace to store the data, the first processor reads the status signaloutputted by the exclusive mailbox of the second processor, anddetermines, according to the status signal, whether the exclusivemailbox of the second processor has the sufficient storage space tostore the data.
 11. The processor error checking method as claimed inclaim 10, wherein when the exclusive mailbox of the second processor hasreceiving the data, the exclusive mailbox of the second processor stopsand resets the timing to zero, and sends an interrupt signal to thesecond processor, and after receiving the interrupt signal, the secondprocessor reads the data in the exclusive mailbox through the exclusivechannel.
 12. The processor error checking method as claimed in claim 11,wherein each of the exclusive mailboxes further comprises: a controlregister for setting an interrupt condition of the exclusive mailbox;and a mailbox controller for managing the storage space as well asgenerating the timeout signal, the interrupt signal and the statussignal.